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| Paper IPM / Computer Science / 10808 |
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In this paper, we propose the first interrelated power and latency mathematical model for the Networks-on-Chip (NoC) architecture with mesh topology. Through an analytical approach, we show the importance of tile selection in which the hot (frequently accessed) IP core is mapped. Taking into account the effect of blocking in both power and latency models, causes the estimated values to be more accurate. Simulation results confirm the reasonable accuracy of the proposed model. The major output of the model which is the average energy consumption per cycle in the whole network is the efficacious parameter that is most important and must be used by NoC designers.
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